Stacked capacitors are widely used in dynamic random access memory chips (DRAM). But several problems have been identified with stacked capacitors, including a trade off between capacitance and surface topology. As the size of DRAM cells diminishes with each new generation of technology, improvement is needed in capacitor design to maintain the needed level of capacitance for each cell. Two general techniques have emerged, roughening and multiple stacked layers or fins.
Several techniques have been described for providing structures to texture or roughen the surface of polysilicon electrodes used as capacitor plates. Commonly assigned U.S. Pat. No. 5,254,503, to the present inventor, describes several of these prior art techniques and provides a method of achieving subminimum dimension trenches within a capacitor to substantially increase surface area and capacitance.
Alternatively, commonly assigned U.S. Pat. No. 5,160,987, to Pricer et al., describes a capacitor having a large number of fins. However, adding fins can significantly increase stack height and surface topology to the detriment of subsequent processing steps.
A structure which provides a large number of fins without substantially increasing stack height would be valuable and is provided in this invention.